Fabrication of a variety of device types such as a plurality of field-effect transistors (FETs) to support multiple voltage domains within a single integrated circuit (IC) can drive diverse device topologies for complementary metal oxide semiconductor (CMOS) device structures comprising the IC. Multiple photo exposure and multiple etch processes to support shallow trench isolation of the plurality of FETs or to form contacts of various heights to align with topologies of CMOS devices can add overhead to IC fabrication, produce unintended topologies requiring additional fabrication steps to eliminate, introduce defects, degrade device performance, etc.